The present invention relates to semiconductor integrated circuits and, more particularly, to an input-output (I/O) buffer, which is capable of interfacing with voltages higher than its I/O voltage.
CMOS integrated circuits are typically provided with tri-state I/O buffers that are selectively operable between a low-impedance drive mode and a high-impedance, tri-state mode in which the buffers appear transparent to the output pad terminals with which they are connected. Advancements in semiconductor fabrication technology enable the geometries of semiconductor devices to be progressively reduced so that more devices can fit on a single integrated circuit. As a result, core voltages of integrated circuits are being reduced to prevent damage to the small devices and to reduce overall power consumption of the integrated circuit. For example, power supplies are now being reduced from 5V to 3.3V, from 3.3V to 2.5V, and from 2.5V to 1.8V.
However, low voltage CMOS devices are often interconnected at a board level to integrated circuits having older technology and operating at higher core voltages such as 3.3V or 5V. It is therefore desirable to provide an I/O buffer that is tolerant to pad voltages that are larger than the I/O voltage without exceeding the tolerance levels of the devices within the buffer and without drawing leakage current from the pad terminal while in the tri-state mode.